Subnanosecond Time-to-Digital Converter Implemented in a Kintex-7 FPGA

摘要

Time-to-digital converters (TDCs) are used in various fields, includinghigh-energy physics. One advantage of implementing TDCs in field-programmablegate arrays (FPGAs) is the flexibility on the modification of the logics, whichis useful to cope with the changes in the experimental conditions. Recent FPGAsmake it possible to implement TDCs with a time resolution less than 10 ps. Onthe other hand, various drift chambers require a time resolution of O(0.1) ns,and a simple and easy-to-implement TDC is useful for a robust operation. Hereinan eight-channel TDC with a variable bin size down to 0.28 ns is implemented ina Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling schemewith quad phase clocks synchronised with an external reference clock.Calibration of the bin size is unnecessary if a stable reference clock isavailable, which is common in high-energy physics experiments. Depending on thechannel, the standard deviation of the differential nonlinearity for a 0.28 nsbin size is 0.13-0.31. The performance has a negligible dependence on thetemperature. The power consumption and the potential to extend the number ofchannels are also discussed.